1. Field of the Disclosure
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress memorization techniques to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Integrated circuits typically include a very large number of circuit elements, such as transistors, capacitors and the like, wherein field effect transistors are frequently used as transistor elements, in particular when complex digital circuit portions are considered. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches for forming field effect transistors due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors.
The continuing shrinkage of the transistor dimensions, such as reducing the channel length and thus the channel resistance per unit length, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same crystalline configuration may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is therefore an extremely promising approach for further device generations, since strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast, powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
In some approaches, external stress created by, for instance, permanent overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided, for instance, by contact layers, spacers and the like into the channel region to create the desired strain therein. Thus, for different transistor types, differently stressed overlayers have to be provided, which may result in a plurality of additional process steps, wherein, in particular, any additional lithography steps may contribute significantly to the overall production costs.
In still a further approach, a substantially amorphized region may be formed adjacent to the gate electrode at an intermediate manufacturing stage, which may then be re-crystallized in the presence of a “rigid” overlying layer formed above the transistor area. During the anneal process for re-crystallizing the lattice, the growth of the crystal will occur under specific stress conditions created by the overlayer and result in a tensile strained crystal, which may be advantageous for N-channel transistors, as explained above. After the re-crystallization, the sacrificial stress layer may be removed, wherein, nevertheless, a certain amount of strain may be “conserved” in the re-grown lattice portion. This effect is generally known as stress memorization. Although the exact mechanism is not yet fully understood, it is believed that, during the anneal process, the interaction of the rigid overlayer with the highly damaged or amorphous silicon material may suppress a volume reduction of the re-crystallizing silicon lattice, which may therefore remain in a tensile-strained state.
However, the creation of a tensile-strained lattice in the vicinity of the channel region may result in a performance degradation of P-channel transistors, since a uniaxial tensile strain component in the channel region of the P-channel transistor may result in a reduced hole mobility. Therefore, the stress memorization technique is frequently applied in a selective manner by patterning the rigid cap layer so as to expose the P-channel transistors prior to performing the anneal process, thereby adding an additional cost-intensive lithography process, as will be described with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a P-channel transistor 150p and an N-channel transistor 150n, which are formed above a substrate 101 having formed thereabove a silicon-based semiconductor layer 102. The substrate 101, in combination with the silicon-based semiconductor layer 102, may represent a bulk configuration, that is, if the semiconductor layer 102 may represent a part of a crystalline material of the substrate 101, while in other cases a silicon-on-insulator (SOI) configuration may be provided in which the silicon-based semiconductor layer 102 may be formed on an insulating layer (not shown), which may frequently be referred to as a buried insulating layer.
In the manufacturing stage shown in FIG. 1a, the P-channel transistor 150p and the N-channel transistor 150n are shown to have substantially the same configuration, although it should be appreciated that the transistors 150p, 150n may at least differ from each other with respect to the conductivity type, i.e., the type of dopant species used for defining the transistor characteristics of the respective transistors. Thus, the transistors 150p, 150n may comprise a gate electrode 151 formed above a channel region 154 and separated therefrom by a gate insulation layer 152. Moreover, a sidewall spacer structure 153 may be formed on sidewalls of the gate electrode 151. Furthermore, drain and source regions 155 are formed in respective portions of the silicon-based layer 102 in combination with appropriately designed extension regions 155e, thereby defining, in combination with the channel region 154, PN junctions as are required for the transistor behavior of the devices 150p and 150n. In the manufacturing stage shown, the drain and source regions 155 and the extension regions 155e are still in a highly non-crystalline state, that is, at least the drain and source regions 155 may exhibit heavy lattice damage or may be in a substantially amorphous state. As previously explained, after re-crystallizing a heavily damaged or amorphous drain and source region 155 in the presence of an appropriate cap layer, such as a silicon nitride layer, typically a tensile strain may be generated in the channel region 154, thereby significantly enhancing the transistor characteristics of the transistor 150n for a certain crystallographic configuration of the silicon-based layer 102. On the other hand, a tensile strain in the channel region 154 of the P-channel transistor 150p may not be desired, since a certain amount of uniaxial tensile strain in the P-channel transistor 150p may negatively affect the charge carrier mobility therein, as previously explained.
The semiconductor device 100 as shown in FIG. 1a may be formed in accordance with well-established conventional manufacturing techniques. That is, after defining appropriately desired active regions, that is, portions in the silicon-based semiconductor layer 102 having an appropriate size and dopant concentration for forming therein P-channel transistors or N-channel transistors, which may be accomplished on the basis of the formation of isolation structures (not shown), such as trench isolation structures, and establishing a desired dopant concentration as required for P-channel transistors and N-channel transistors, the gate insulation layers 152 and the gate electrodes 151 may be formed. For this purpose, sophisticated deposition and/or oxidation techniques may be used for forming the gate insulation layers 152, followed by the deposition of a gate electrode material. Subsequently, advanced lithography techniques may be used for patterning the gate electrode structures 151 in combination with the gate insulation layers 152. Thereafter, implantation processes may be performed, for instance using an offset spacer (not shown) to define the position of the extension regions 155e with respect to the channel region 154. It should be appreciated that other implantation processes may be performed, such as pre-amorphization implantation for substantially amorphizing exposed portions of the silicon-based layer 102 down to a specified depth. In sophisticated applications, the transistor characteristics may also be determined on the basis of halo implantation processes, during which a dopant species may be introduced having the inverse conductivity type compared to the conductivity type of the extension regions 155e and the drain and source regions 155. It should be appreciated that, during respective implantation processes, such as the halo implantation and the implantation for forming the extension regions 155e for one type of transistors, for instance for the transistor 150p, the transistor 150n is masked by a resist mask which is then removed and replaced by a resist mask covering the transistor 150p and exposing the transistor 150n, which may then receive the appropriate dopant species. Next, the spacer structure 153 may be formed by depositing a liner material, such as silicon dioxide followed by the deposition of a silicon nitride material, which may then be etched to obtain the spacer structure 153. Thereafter, the transistors 150p, 150n are again appropriately masked by photolithography to introduce the respective dopant species for forming the drain and source regions 155 of different conductivity types for the transistors 150p, 150n. 
FIG. 1b schematically illustrates the device 100 in an advanced manufacturing stage in which a cap layer 103 comprised of silicon nitride, in combination with an etch stop liner 104, is formed above the transistors 150p, 150n which may be used as a rigid material for selectively creating a tensile strain in the transistor 150n during a respective anneal process. Since a corresponding tensile strain may not be desirable in the transistor 150p, a resist mask 105 is provided so as to expose the transistor 150p. The liner 104 and the cap layer 103 may be formed on the basis of well-established process techniques, such as plasma enhanced chemical vapor deposition (PECVD), followed by a photolithography process for forming the resist mask 105. Thereafter, the exposed portion of the cap layer 103 may be removed on the basis of the resist mask 105 by using appropriate etch chemistries having high selectivity with respect to the etch stop liner 104. For this purpose, well-established wet chemical techniques or plasma assisted removal techniques are available.
FIG. 1c schematically illustrates the device 100 after the above-described process sequence, and with the resist mask 105 removed. Moreover, the device 100 is subjected to an anneal process 106, such as a rapid thermal anneal process (RTA) or any other advanced anneal techniques, such as flashlight anneal or laser anneal techniques that are performed on the basis of appropriately selected process parameters so as to activate the dopant species in the drain and source regions 155 and the extension regions 155e, thereby also substantially re-crystallizing these portions. As explained above, during the anneal process 106, the presence of the cap layer 103 above the transistor 150n may result in a strained state of significant portions of the drain and source regions 155 and 155e, thereby resulting in a desired high strain 154S in the channel region 154. Although the reason for the creation of the strained re-crystallization of the drain and source regions 155 is not yet fully understood, it is believed that the cap layer 103 may act as a rigid material, which may suppress the reduction in volume in the drain and source regions during the re-crystallization process, thereby resulting in a strained state. After removal of the cap layer 103, the tension may still remain, thereby permanently creating the strain 154S in the channel region 154. On the other hand, the drain and source regions 155 and the extension regions 155e in the P-channel transistor 150p may substantially re-grow in a non-strained state, thereby maintaining the channel region 154 in a substantially stress-neutral state. After the anneal process 106, the cap layer 103 may be removed, for instance, by selectively etching the material of the layer 103 with respect to the liner 104 using well-established wet chemical techniques or plasma assisted processes. Thereafter, the liner 104 may be removed and the devices may be prepared for the formation of metal silicide regions.
FIG. 1d schematically illustrates the semiconductor device 100 with metal silicide regions 156 formed in the drain and source regions 155 and in the gate electrodes 151. To this end, well-established silicidation process sequences may be used.
Consequently, by appropriately patterning the cap layer 103 prior to the anneal process 106, the strain 154S may be selectively provided in the N-channel transistor 150n, thereby enhancing the overall transistor characteristics thereof, while substantially not negatively influencing the P-channel transistor 150p, which may have provided therein appropriate strain-inducing mechanisms (not shown), which may provide a different type of strain, or the transistor 150p may be maintained in a substantially strain-neutral state, depending on the device requirements. On the other hand, the additional photolithography step required for patterning the layer 103 may contribute to process complexity, as photolithography steps are typically one of the most cost-intensive process steps due to the high investment costs and cost of ownership for advanced lithography equipment in combination with low cycle times.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.